1. Field of the Invention
The present invention relates to a multi-series inverter arrangement and, in particular, relates an improvement in a gate driving circuit in a multi-series inverter arrangement which controls turn on and turn off of switching elements such as gate turn-off thyristers (hereinafter abbreviated as GTO) for a multi-series inverter.
2. Description of Related Art
An example of conventional multi-series inverters is disclosed such as in JP-A-56-74088 (1981). FIG. 1 is a diagram illustrating a main circuit of the multi-series inverter. In the drawing, numeral 11 is a DC power source, and smoothing capacitors 12 and 13 connected in series are connected to the DC power source 11 in parallel. The mutual juncture point of these two smoothing capacitors 12 and 13 is used as a neutral point of the DC power source 11. A switching circuit thereof is constituted by GTOs S1U through S4W, flywheel diodes D1U through D4W and clamping diodes CD1U through CD2W for clamping respective output terminals U, V and W at a neutral potential.
The GTOs S1U through S4W constituting the multi-series inverter are controlled turned on and turned off by on and off signals provided from a control circuit (not shown) and the GTOs S1 and S3, and the GTOs S2 and S4 are designed to operate respectively as a set of inverters and are controlled to turn on and turn off in a conjugate relationship with each other. As a result, the output voltage at the output terminals of the multi-series inverter is controlled depending upon the on condition of the respective switching elements as illustrated in FIG. 2. For example, noting U phase, when the switching elements S1U and S2U are turned on (and the switching elements S3U and S4U are turned off), the potential at the output terminal U is rendered at +E. Contrary thereto, when the switching elements S3U and S4U are turned on (and the switching elements S1U and S2U are turned off), the potential at the output terminal U is rendered at -E. Further, when the switching elements S2U and S3U are turned on (and the switching elements S1U and S4U are turned off), the output terminal U is connected to the juncture point of the smoothing capacitors 12 and 13 via the switching elements S2U and S3U and the clamping diodes CD1U and CD2U, and is fixed at zero potential of the power source neutral point. Simultaneous turn on of the switching elements S1U and S4U is inhibited. As a result of the above explained operation of the switching circuit, potential at the output terminal U varies between +E, 0 and -E.
FIG. 3 shows a waveform diagram of a gate current supplied to GTOs from a gate driving circuit for turning on the GTOs which is illustrated, for example, on page 24 in "Semiconductor Power Converter Circuit" (edited by Special Committee for Investigating Semiconductor Power Conversion System for the Institute of Electrical Engineers of Japan, 1987). When an on signal is applied to a GTO from a control circuit, at first a high gate drive forward current IFG1 is provided thereto and subsequently a wide width gate forward current IFG2 is provided thereto. Based upon "Characteristics of GTO of 4.5 kV and 2000 A", a reference paper SPC-83-29 prepared by Semiconductor Power Conversion Study Committee for the Institute of Electrical Engineers of Japan, 1983, in case of a GTO of 4.5 kV and 2000 A, for example, IFG1=25 A and IFG2=2 A are proposed. Accordingly, a gate driving circuit is constituted in such a manner that when an on signal is applied thereto the gate driving circuit causes a high gate drive forward current IFG1 to flow until the GTO is turned on and thereafter a wide width gate forward current IFG2 is caused to flow until the signal from the control circuit is changed into an off signal.
FIG. 4 shows an example of gate driving circuits which cause the gate current to flow as illustrated in FIG. 3. When an on signal is applied thereto, a switch SW1 is closed. As a result, electric charges stored in the capacitor C via a resistor R1 are discharged via a resistor R2 and are provided to the GTO as a high gate drive forward current IFG1 and subsequently a wide width gate forward current IFG2 is provided thereto from an on power source E1. When turning off the GTO, the switch SW1 is opened and a switch SW2 is closed to reverse bias the GTO with an off power source E2. As will be apparent from FIG. 3, the high gate drive forward current IFG1 cannot be caused to flow except for the moment when an on signal is applied. Further, switching elements such as transistors and FETs are used for the switches SW1 and SW2.
A reason, which necessitates a large gate current such as the high gate drive forward current when a GTO is required to be turned on, is that if the gate current is small at the moment when a current suddenly begins to flow through the GTO, areas of an on condition do not easily expand over the GTO and a current concentration therein is induced which likely causes a break-down of the GTO.
Accordingly, for a GTO through which no current flows although an on signal is applied thereto, a high gate drive forward current has to be theoretically provided at the moment when a current begins to suddenly flow depending upon the circuit condition. However, in the conventional gate driving circuit no current except for the wide width gate forward current can be caused to flow at the moment. For this reason, under these conditions even if a current tends to flow suddenly, the GTO likely turns off at once due to insufficient on condition thereof and there arises a problem that a voltage between the anode and cathode of the GTO is induced. Such problem is particularly significant with regard to a high speed GTO having a short turn off time. Hereinbelow, this phenomenon is explained in detail with reference to drawings.
FIG. 5 is a circuit diagram showing only a portion for one phase of the multi-series inverter illustrated in FIG. 1. In the multi-series inverter, the GTOs S1 and S3 and the GTOs S2 and S4 are respectively operated to turn on and turn off in a conjugate relationship with each other as a set of inverter, therefore as illustrated in FIG. 6 there exists three kinds of switching conditions (1).about.(3) of the GTOs S1 through S4 and four kinds of changes in switching conditions 1 through 4. Among these changes in switching conditions a phenomenon, wherein the GTO tends to turn off, in other words, a phenomenon that a voltage is induced at the GTO (hereinafter called as "incomplete on phenomenon") because the GTO is not sufficiently moved into an on condition when a current having a high di/dt (which will be explained later in detail) flows through the GTO, is caused under the following two conditions. The first one is caused under a condition that the GTOs S1 and S2 in FIG. 5 are in an on condition (the condition (2) in FIG. 6) and a load current is flowing through the flywheel diodes D1 and D2 in the direction of an arrow 15 in FIG. 5 when the GTO S1 is turned off and the GTO S3 is turned on (the change in switching condition 2 in FIG. 6), and the other is caused under a condition that the GTOs S3 and S4 are in an on condition (the condition (3) in FIG. 6) and a load current is flowing through the flywheel diodes D3 and D4 in the direction of an arrow 16 in FIG. 5 when the GTO S4 is turned off and the GTO S2 is turned on (the change in switching condition 4). These two changes in switching conditions are hereinafter called respectively as mode 1 and mode 2.
Current flows during the mode 1 are illustrated in FIG. 7. When the GTO S1 is turned off and the GTO S3 is turned on, the load current flowing through the flywheel diodes D1 and D2 is commutated toward the GTO S3 and the clamping diode CD2 in the direction of an arrow 21 and a current from the smoothing capacitor 12 flowing through the flywheel diode D1 for recovering the same and a snubber circuit 20 for the GTO S1 as shown by arrow 22 flows through the GTO S2. This current, as indicated by arrow 22, is one which builds up suddenly at a di/dt of about 100 A/.mu.s and is caused to flow through the GTO S2 through which no current has flowed until that moment although an on signal has been provided thereto. FIG. 8 shows a voltage waveform induced between the anode and gate of the GTO S2 and the current waveform thereof at that moment. As seen from the drawing a voltage is induced at the GTO S2 and the induced voltage .DELTA.V when di/dt is 100 A/.mu.s reaches upto 200 V. Such voltage induction leads to an increase of switching element damage and, in some cases, leads to a breakdown of the switching elements which is undesirable.
Current flows during the mode 2 are illustrated in FIG. 9. When the GTO S4 is turned off and the GTO S2 is turned on, a load current flowing through the flywheel diodes D3 and D4 is commutated toward the clamping diode CD1 and the GTO S2 in the direction of an arrow 23 and a current from the smoothing capacitor 13 flowing through the flywheel diode D4 for recovering the same and a snubber circuit 20 for the GTO S4 as shown by an arrow 24 flows through the GTO S3. This current as indicated by arrow 24 is one which, like in the mode 1, builds up suddenly at a di/dt of about 100 A/.mu.s and a voltage as illustrated in FIG. 8 is also induced at the GTO S3. In this instance like in the mode 1, such voltage induction leads to an increase of switching element damage and, in some cases, leads to a breakdown of the switching elements which is undesirable.
Although there was a similar mode in a conventional two level inverter wherein a current begins to flow through a GTO through which no current has flowed until then, nevertheless an on signal is applied thereto, and the current variation was a slow one (di/dt of about 1 A/.mu.s) which is determined by a load and there arise no such problems.
FIG. 10 shows a relationship between voltage .DELTA.V induced at GTO due to incomplete on phenomenon and gate current provided thereto using di/dt of a current flowing through the GTO as a parameter. For a gate current 7 A which is flown as a wide width gate forward current in a conventional gate driving circuit, no voltage is induced at the GTO with di/dt=1 A/.mu.s as seen from FIG. 10, contrary thereto, with di/dt=100 A/.mu.s a voltage of about 200 V is induced at the GTO.